Laminated chip electronic component, board for mounting the same, and packing unit thereof
US8934215B2 · kind B2 · utility
4Cited by
2References
15Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Dec 13, 2012 |
| Grant date | Jan 13, 2015 |
| Priority date | — |
| Expiry date | Apr 5, 2033 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY02P70/50
- WIPO fieldElectrical machinery, apparatus, energy
- WIPO sectorElectrical engineering
Abstract
A laminated chip electronic component includes: a ceramic body including internal electrodes and dielectric layers; external electrodes covering end portions of the ceramic body in length direction; an active layer in which the internal electrodes are disposed in opposing manner, while having the dielectric layers interposed therebetween, to form capacitance; and upper and lower cover layers formed on upper and lower portions of the active layer in thickness direction, the lower cover layer thicker than the upper cover layer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.