Method for reducing data alignment delays
US8934592B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Jan 24, 2013 |
| Grant date | Jan 13, 2015 |
| Priority date | — |
| Expiry date | Feb 23, 2033 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L25/14
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
A method is provided for synchronizing binary data transmitted in parallel via N channels. The method comprises performing at the receiver side, a data-clock-alignment for the data in the N channels by selecting an optimal reference channel to which no delay will be added, and adding an appropriate delay to each of the remaining channels, until their respective centers of valid data portions are aligned to each other, and associating clock edges with the centers of the valid data portions. The method is characterized in that the alignment is performed regardless to whether binary word alignment is simultaneously achieved or not, and wherein the optimal reference channel allows aligning the centers of valid data of all the channels while adding a minimal delay to a worst channel from among the remaining channels, wherein the worst channel carries valid data portions which are maximally shifted from those of the reference channel.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.