Memory apparatus
US8935460B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jul 12, 2012 |
| Grant date | Jan 13, 2015 |
| Priority date | — |
| Expiry date | Aug 7, 2033 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2212/7208
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A memory apparatus includes first memory chip and second memory chip; and a control unit configured to manage a global reserved area, a first virtual area for the first memory chip, and a second virtual area for the second memory chip, wherein the first virtual area includes a first user area and a first reserved area, the second virtual area includes a second user area and a second reserved area, the global reserved area includes a first plurality of reserved blocks corresponding to the first reserved area and a second plurality of reserved blocks corresponding to the second reserved area, and the control unit is configured to assign a second virtual block included in the global reserved area to the first user area if the control unit detects a first virtual block included in the first user area is a bad block.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.