Method and apparatus for optimizing power and latency on a link
US8935578B2 · kind B2 · utility
2Cited by
4References
30Claims
0Family size
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Key dates
| Filing date | Sep 29, 2012 |
| Grant date | Jan 13, 2015 |
| Priority date | — |
| Expiry date | Mar 23, 2033 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY02D10/00
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An apparatus and method are disclosed to optimize the latency and the power of a link operating inside a processor-based system. The apparatus and method include a latency meter built into a queue that does not rely on a queue-depth threshold. The apparatus and method also include feedback logic that optimizes power reduction around an increasing latency target to react to sluggish re-provisioning behavior imposed by the physical properties of the link.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.