Delay method, circuit and integrated circuit
US8937500B2 · kind B2 · utility
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2References
16Claims
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Key dates
| Filing date | Dec 17, 2013 |
| Grant date | Jan 20, 2015 |
| Priority date | — |
| Expiry date | Dec 17, 2033 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K5/14
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
This document discusses, among other things, a delay circuit, in which a first register is written with a delay reference code, a second register is written with a delay factor, a control unit determines a corresponding delay ratio in a storage unit based on the delay factor in the second register, and sends the determined delay ratio to a first digital timing unit, the first digital timing unit determines a delay reference time based on the delay reference code in the first register, multiplies the delay reference time by the delay ratio to result in a desired delay time, and generates a delay.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.