Write level training using dual frequencies in a double data-rate memory device interface
US8937846B2 · kind B2 · utility
4Cited by
5References
20Claims
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Key dates
| Filing date | May 9, 2013 |
| Grant date | Jan 20, 2015 |
| Priority date | — |
| Expiry date | Aug 15, 2033 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2207/2254
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A write leveling calibration system and method for double data-rate dynamic random access memory includes performing write leveling at two different frequencies to determine to which of two successive rising clock cycle edges each data strobe signal would be aligned as a result of applying the write leveling delay determined by the write-leveling procedure. The determination can then be used to ensure that the data strobe signals of all source synchronous groups are aligned with the same edge of the clock signal.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.