High speed gain and phase recovery in presence of phase noise
US8938037B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 13, 2013 |
| Grant date | Jan 20, 2015 |
| Priority date | — |
| Expiry date | Mar 13, 2033 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L27/3809
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
A circuit for reducing phase errors in a digital communication systems signal is provided. The circuit comprises a demodulator block, a feed-forward path, a feed-back path, and a slicer. The demodulator block generates a plurality of samples from the signal and determines for each sample a corresponding phase error. The feed-forward path is configured to reduce in the signal a high frequency component of the phase errors. The feed-back path configured to reduce in the signal a low frequency component of the phase errors. The slicer selectively forwards phase errors to the feed-forward path or the feed-back path based on a respective magnitude of the phase error when operating in a decision-directed mode.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.