Timing driven routing for noise reduction in integrated circuit design
US8938702B1 · kind B1 · utility
3Cited by
9References
20Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Dec 19, 2013 |
| Grant date | Jan 20, 2015 |
| Priority date | — |
| Expiry date | Dec 19, 2033 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2119/12
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A mechanism is provided in a data processing system for timing-driven routing for noise reduction in integrated circuit design. Responsive to performing timing driving routing on an integrated circuit design, the mechanism identifies a set of noise-critical nets in the integrated circuit design. The mechanism performs timing driven routing on the integrated circuit design with noise constraints based on the set of noise-critical nets.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.