Capacitorless memory device
US8941173B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Feb 25, 2013 |
| Grant date | Jan 27, 2015 |
| Priority date | — |
| Expiry date | Mar 12, 2033 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10B12/00
Abstract
According to an example embodiment of inventive concepts, a capacitorless memory device includes a capacitorless memory cell that includes a bit line on a substrate; a read transistor, and a write transistor. The read transistor may include first to third impurity layers stacked in a vertical direction on the bit line. The first and third layers may be a first conductive type, and the second impurity layer may be a second conductive type that differs from the first conductive type. The write transistor may include a source layer, a body layer, and a drain layer stacked in the vertical direction on the substrate, and a gate line that is adjacent to a side surface of the body layer. The gate line may be spaced apart from the side surface of the body layer. The source layer may be adjacent to a side surface of the second impurity layer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.