Helical spiral inductor between stacking die
US8941212B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Feb 6, 2013 |
| Grant date | Jan 27, 2015 |
| Priority date | — |
| Expiry date | May 11, 2033 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D1/20
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
The present disclosure relates to a multi-level integrated inductor that provides for a good inductance and Q-factor. In some embodiments, the integrated inductor has a first inductive structure with a first metal layer disposed in a first spiral pattern onto a first IC die and a second inductive structure with a second metal layer disposed in a second spiral pattern onto a second IC die. The first IC die is vertically stacked onto the second IC die. A conductive interconnect structure is located vertically between the first and second IC die and electrically connects the first metal layer to the second metal layer. The conductive interconnect structure provides for a relatively large distance between the first and second inductive structures that provides for an inductance having a high Q-factor over a large range of frequencies.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.