Shared control logic for multiple queues
US8942248B1 · kind B1 · utility
Assignee
Inventor
Key dates
| Filing date | Apr 19, 2010 |
| Grant date | Jan 27, 2015 |
| Priority date | — |
| Expiry date | Sep 3, 2031 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04J3/062
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
Methods, integrated circuits, and computer programs for managing a communication path carrying multiple channels are presented. Each channel includes a first-in first-out (FIFO) queue. In one method, the time difference between the start of a cycle for receiving data in a particular channel and a start of a cycle for transmitting data in the same particular channel is identified. Further, the method includes an operation for buffering arriving data in the communication path. The arriving data is buffered for an amount of time equal to the identified time difference, and the result is delayed data. FIFO registers are loaded from memory, which includes loading FIFO control and status data for a single FIFO queue, where the single FIFO queue is associated with the current channel of the produced delayed data at any time. Additionally, method includes an operation for processing contemporaneously read and write requests for the single FIFO queue using the loaded FIFO registers.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.