Partial response equalizer and related method
US8942319B2 · kind B2 · utility
1Cited by
1References
33Claims
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Key dates
| Filing date | Mar 25, 2011 |
| Grant date | Jan 27, 2015 |
| Priority date | — |
| Expiry date | Nov 27, 2033 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L2025/03369
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
A multi-phase partial response receiver supports various incoming data rates by sampling PrDFE output values at a selected one of at least two clock phases. The receiver includes a calibration circuit that performs a timing analysis of critical data paths in the circuit, and this analysis is then used to select the particular clock phase used to latch the output values. These techniques permit the multiplexer outputs from for each phase of the partial response receiver to directly drive selection of a multiplexer for the ensuing phase, i.e., by avoiding regions of instability or uncertainty in the respective multiplexer outputs.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.