Latency sensitive software interrupt and thread scheduling
US8943252B2 · kind B2 · utility
10Cited by
7References
20Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Aug 16, 2012 |
| Grant date | Jan 27, 2015 |
| Priority date | — |
| Expiry date | Feb 7, 2033 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2209/5021
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Various embodiments provide an ability to schedule latency-sensitive tasks based, at least in part, upon one or more processor cores usage metrics. Some embodiments gather information associated with whether one or more processor cores are in a heavily loaded state. Alternately or additionally, some embodiments gather information identifying latency-sensitive tasks. Task(s) can be (re)assigned to different processor core(s) for execution when it has been determined that an originally assigned processor core has exceeded a usage threshold.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.