Methods and structure for accounting for connection resets between peripheral component interconnect express bridges and host devices
US8943255B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | May 29, 2012 |
| Grant date | Jan 27, 2015 |
| Priority date | — |
| Expiry date | Jun 19, 2033 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F13/385
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Methods and structure for accounting are provided for enhancing communications via a PCIE bridge. The bridge comprises a host interface that manages communications with a host device, and a PCIE interface that provides Memory Read Requests (MRds) to a PCIE device and receives Memory Read Completions (MRCs) from the PCIE device. The bridge also comprises a control unit that inserts tag information into the MRds. The control unit detects a reset of the host interface and revises the tag information inserted into the MRds responsive to detecting the reset. Additionally, the control unit analyzes tag information of received MRCs to determine whether it is the revised tag information or is old tag information, returns completion data from MRCs having the revised tag information to the host device, and discards completion data from received MRCs having the old tag information.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.