Multi-core processor system configured to constrain access rate from memory
US8943287B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Jul 17, 2012 |
| Grant date | Jan 27, 2015 |
| Priority date | — |
| Expiry date | Jan 10, 2033 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F13/1652
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A multi-core processor system includes a number of cores, a memory system, and a common access bus. Each core includes a core processor; a dedicated core cache operatively connected to the core processor; and, a core processor rate limiter operatively connected to the dedicated core cache. The memory system includes physical memory; a memory controller connected to the physical memory; and, a dedicated memory cache connected to the memory controller. The common access bus interconnects the cores and the memory system. The core processor rate limiters are configured to constrain the rate at which data is accessed by each respective core processor from the memory system so that each core processor memory access is capable of being limited to an expected value.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.