Parallel read functional unit for microprocessors
US8943297B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jan 8, 2013 |
| Grant date | Jan 27, 2015 |
| Priority date | — |
| Expiry date | Jan 8, 2033 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L2209/12
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A functional unit is provided which allows for fast, parallel data read, write, and manipulation operations. The functional unit includes first and second source registers for receiving first and second data items to be processed by the functional unit, a plurality of memory tables, a combinational logic circuit, and a decoder. Each of the tables is indexed by an index comprising a portion of the first data item received by the first source register. The combinational logic circuit receives lookup results, and processes the lookup results and the second data item in the second source register to produce a result data item. The decoder circuit extracts an operational code from an instruction supplied to the functional unit, decodes the operational code, and controls the combinational logic circuit in accordance with the operational code.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.