Extended liner for localized thick copper interconnect
US8946896B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 31, 2009 |
| Grant date | Feb 3, 2015 |
| Priority date | — |
| Expiry date | Jul 26, 2031 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/0002
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A dielectric layer overlies a semiconductor substrate. The substrate has components and appropriate contacts formed therein. The dielectric layer electrically insulates the substrate and components from overlying conductive interconnect layers. A barrier layer is arranged over the dielectric layer to isolate the interconnect layers from other structures. A copper layer is then deposited over the barrier layer and thick interconnect lines having a first width and a first height are realized. Then, the barrier layer is etched using one of many alternative techniques. The barrier layer has a second width and a second height wherein the second width of the barrier liner is selected to be greater than the first width of the thick copper interconnect.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.