Substrate vias for heat removal from semiconductor die
US8946904B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Aug 27, 2010 |
| Grant date | Feb 3, 2015 |
| Priority date | — |
| Expiry date | Jun 26, 2031 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/13091
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A substrate comprising a plurality of layers, a first side and a second side; and a via extending through the substrate from the first side to the second side. The via comprises:a first substrate via extending through a first layer of the plurality of layers, the first substrate via having a first cross-sectional area; a first capture pad disposed under the first substrate via, wherein the first capture pad physically contacts the first substrate via; a second substrate via extending through a second layer of the plurality of layers, the second substrate via physically contacting the first capture pad, the second substrate via having a second cross-sectional area that is greater than the first cross-sectional area; and a second thermal and electrical contact pad disposed under the second dielectric layer, wherein the second contact pad physically contacts the second substrate via.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.