Latch array utilizing through device connectivity
US8947120B2 · kind B2 · utility
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25Claims
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Key dates
| Filing date | Sep 13, 2012 |
| Grant date | Feb 3, 2015 |
| Priority date | — |
| Expiry date | May 1, 2033 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F30/30
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A circuit for implementing latch array functions on an integrated circuit. Portions of the logic devices included in the implementation of the latch array functions that are controlled by a common signal, may be arranged in a particular alignment. A single layer uni-directionally conductive material may connect the common signal to the logic devices.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.