Patent · US Active

Stacked clock distribution for low power devices

US8947149B1 · kind B1 · utility

5Cited by

1References

20Claims

0Family size

Assignee

NXP B.V. · NL

Inventors

Ajay Kapoor · Eindhoven, NL
Ralf Malzahn · Seevetal, DE
Rinze Ida Mechtildis Peter Meijer · Herkenbosch, NL
Peter Thueringer · Graz, AT

Key dates

Filing date	Dec 20, 2013
Grant date	Feb 3, 2015
Priority date	—
Expiry date	Dec 20, 2033

Classification

Technology area (CPC G)Physics
CPC primaryG06F1/10
WIPO fieldBasic communication processes
WIPO sectorElectrical engineering

Abstract

Embodiments of a clock distribution device and a method of clock distribution are described. In one embodiment, a clock distribution device includes a stacked clock driver circuit configured to perform clock signal charge recycling on input clock signals that swing between different voltage ranges and a load circuit. The stacked clock driver circuit includes stacked driver circuits configured to generate output clock signals that swing between the different voltage ranges. The load circuit includes load networks of different semiconductor types. Each of the load networks are configured to be driven by one of the output clock signals. Other embodiments are also described.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.