High speed and high jitter tolerance dispatcher
US8948215B2 · kind B2 · utility
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22Claims
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Key dates
| Filing date | Apr 18, 2012 |
| Grant date | Feb 3, 2015 |
| Priority date | — |
| Expiry date | Dec 15, 2032 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03M9/00
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A deserializer circuit includes demultiplexer circuitry configured to receive serial data from an input and output a plurality of divided data outputs, and multiplexer circuitry configured to receive a first logic level at a first input of said multiplexer circuitry, and receive a second logic level at a second input of said multiplexer circuitry and receive one of said divided data outputs at a control input of said multiplexer circuitry. The outputs of the multiplexer circuitry produce the received serial data in a parallel form.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.