Incremental lattice reduction systems and methods
US8948318B2 · kind B2 · utility
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5References
20Claims
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Key dates
| Filing date | Dec 14, 2011 |
| Grant date | Feb 3, 2015 |
| Priority date | — |
| Expiry date | May 10, 2033 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L2025/03426
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
An exemplary embodiment of the present invention provides an incremental lattice reduction method comprising: receiving an input signal at a plurality of input terminals; evaluating a reliability assessment condition using a primary symbol vector estimate of at least a portion of the input signal; terminating the incremental lattice reduction method if the reliability assessment condition is satisfied; and if the reliability assessment condition is not satisfied, performing at least one iteration of a lattice reduction detection sub-method to obtain a secondary symbol vector estimate.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.