Method of static phase offset correction for a linear phase detector
US8948332B2 · kind B2 · utility
4Cited by
1References
28Claims
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Key dates
| Filing date | Nov 16, 2012 |
| Grant date | Feb 3, 2015 |
| Priority date | — |
| Expiry date | Mar 9, 2033 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03L9/00
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A method for calibrating a clock and data recovery circuit may include configuring a phase detector as a bang-bang phase detector. The bang-bang phase detector may be used to determine a phase difference between a sampling clock provided by an interpolator and a calibration signal. The phase detector may also be configured as a linear phase detector. While using the linear phase detector, a linear phase detector parameter may be adjusted such that the phase difference between the calibration signal and the sampling clock is zero, while keeping the phase of the sampling clock fixed.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.