Hardware execution driven application level derating calculation for soft error rate analysis
US8949101B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Oct 12, 2011 |
| Grant date | Feb 3, 2015 |
| Priority date | — |
| Expiry date | Nov 15, 2032 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F30/33
- WIPO fieldMeasurement
- WIPO sectorInstruments
Abstract
Mechanisms are provided for predicting effects of soft errors on an integrated circuit device design. A data processing system is configured to implement a unified derating tool that includes a machine derating front-end engine used to generate machine derating information, and an application derating front-end engine used to generate application derating information, for the integrated circuit device design. The machine derating front-end engine executes a simulation of the integrated circuit device design to generate the machine derating information. The application derating front-end engine executes an application workload on existing hardware similar in architecture to the integrated circuit device design and injects a fault into the existing hardware during execution of the application workload to generate application derating information. The machine derating information is combined with the application derating information to generate at least one soft error rate value for the integrated circuit device design.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.