Methods for sustained read and write performance with non-volatile memory
US8949555B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 16, 2011 |
| Grant date | Feb 3, 2015 |
| Priority date | — |
| Expiry date | Jul 22, 2032 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2212/7205
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
In one embodiment of the invention, a memory system includes non-volatile-memory-devices (NVMDs) coupled to memory channels to share busses and a memory controller coupled to the memory channels in communication between the plurality of NVMDs. Each NVMD independently executes a read, write, or erase operation at a time. The memory controller includes channel schedulers to schedule control and data transfers associated with the read, write, and erase operations on the memory channels; and high priority and low priority queues coupled to the channel schedulers. The channel schedulers prioritize operations waiting in the high priority queues over operations waiting in the low priority queues. The channel schedulers further prioritize read operations waiting in either the high priority queue or the low priority queue over write and erase operations waiting in each respective queue.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.