Effective address cache memory, processor and effective address caching method
US8949572B2 · kind B2 · utility
20Cited by
16References
20Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Oct 16, 2009 |
| Grant date | Feb 3, 2015 |
| Priority date | — |
| Expiry date | Sep 16, 2032 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F12/0831
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An effective address cache memory includes a TLB effective page memory configured to retain entry data including an effective page tag of predetermined high-order bits of an effective address of a process, and output a hit signal when the effective page tag matches the effective page tag from a processor; a data memory configured to retain cache data with the effective page tag or a page offset as a cache index; and a cache state memory configured to retain a cache state of the cache data stored in the data memory, in a manner corresponding to the cache index.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.