Patent · US Active

Automatic pipeline parallelization of sequential code

US8949809B2 · kind B2 · utility

7Cited by

1References

20Claims

0Family size

Assignee

International Business Machines Corporation · US

Inventors

Pradeep Varma · New Delhi, IN
Manish Gupta · Kanchinakote, IN
Monika Gupta · New Delhi, IN
Naga Praveen Kumar Katta · Rajamahendravaram, IN

Key dates

Filing date	Mar 1, 2012
Grant date	Feb 3, 2015
Priority date	—
Expiry date	Dec 3, 2032

Classification

Technology area (CPC G)Physics
CPC primaryG06F8/452
WIPO fieldComputer technology
WIPO sectorElectrical engineering

Abstract

A system and associated method for automatically pipeline parallelizing a nested loop in sequential code over a predefined number of threads. Pursuant to task dependencies of the nested loop, each subloop of the nested loop are allocated to a respective thread. Combinations of stage partitions executing the nested loop are configured for parallel execution of a subloop where permitted. For each combination of stage partitions, a respective bottleneck is calculated and a combination with a minimum bottleneck is selected for parallelization.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.