Assist thread for injecting cache memory in a microprocessor

US8949837B2 · kind B2 · utility

Assignee

• International Business Machines Corporation · US

Inventors

• Patrick J. Bohrer · Austin, US
• Orran Krieger · Newton, US
• Ramakrishnan Rajamony · Austin, US
• Michael Rosenfield · Ridgefield, US
• Hazim Shafi · Austin, US
• Balaram Sinharoy · Poughkeepsie, US
• Robert B. Tremaine · Stormville, US

Key dates

• Filing date: Mar 29, 2012
• Grant date: Feb 3, 2015
• Expiry date: Jun 8, 2032

Classification

• Technology area (CPC G): Physics
• CPC primary: G06F12/0862
• WIPO field: Computer technology
• WIPO sector: Electrical engineering

Abstract

A data processing system includes a microprocessor having access to multiple levels of cache memories. The microprocessor executes a main thread compiled from a source code object. The system includes a processor for executing an assist thread also derived from the source code object. The assist thread includes memory reference instructions of the main thread and only those arithmetic instructions required to resolve the memory reference instructions. A scheduler configured to schedule the assist thread in conjunction with the corresponding execution thread is configured to execute the assist thread ahead of the execution thread by a determinable threshold such as the number of main processor cycles or the number of code instructions. The assist thread may execute in the main processor or in a dedicated assist processor that makes direct memory accesses to one of the lower level cache memory elements.