Integrated DRAM memory device
US8952436B2 · kind B2 · utility
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5References
22Claims
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Key dates
| Filing date | Jan 20, 2011 |
| Grant date | Feb 10, 2015 |
| Priority date | — |
| Expiry date | Jun 30, 2031 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/0002
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A DRAM memory device includes at least one memory cell including a transistor having a first electrode, a second electrode and a control electrode. A capacitor is coupled to the first electrode. At least one electrically conductive line is coupled to the second electrode and at least one second electrically conductive line is coupled to the control electrode. The electrically conductive lines are located between the transistor and the capacitor. The capacitor can be provided above a fifth metal level.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.