Chip package and method for forming the same
US8952501B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jul 24, 2013 |
| Grant date | Feb 10, 2015 |
| Priority date | — |
| Expiry date | Jul 24, 2033 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/1461
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
An embodiment of the invention provides a chip package which includes: a semiconductor substrate having an upper surface and a lower surface; a device region or sensing region defined in the semiconductor substrate; a conducting pad located on the upper surface of the semiconductor substrate; at least two recesses extending from the upper surface towards the lower surface of the semiconductor substrate, wherein sidewalls and bottoms of the recesses together form a sidewall of the semiconductor substrate; a conducting layer electrically connected to the conducting pad and extending from the upper surface of the semiconductor substrate to the sidewall of the semiconductor substrate; and an insulating layer located between the conducting layer and the semiconductor substrate.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.