Programmable logic device and semiconductor device
US8952723B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jan 29, 2014 |
| Grant date | Feb 10, 2015 |
| Priority date | — |
| Expiry date | Jan 29, 2034 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K19/017581
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
To provide a PLD having a reduced circuit area and an increased operation speed. In the circuit structure, a gate of a transistor provided between an input terminal and an output terminal of a programmable switch element is in an electrically floating state in a period when a signal is input to the programmable switch element. The structure enables the voltage of a gate to be increased by a boosting effect in response to a signal supplied from programmable logic elements, suppressing a reduction in amplitude voltage. This can reduce a circuit area by a region occupied by a booster circuit such as a pull-up circuit and increase operation speed.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.