Sample and hold circuit with reduced noise
US8952729B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Apr 3, 2013 |
| Grant date | Feb 10, 2015 |
| Priority date | — |
| Expiry date | Apr 3, 2033 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C27/026
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A sample and hold circuit and a method for sampling a signal are disclosed. The sample and hold circuit includes first and second switches, first, second, and third capacitors, and an amplifier. The amplifier receives a signal to be sampled on a first input. The first capacitor is characterized by a first capacitance and has a first terminal connected to an output of the amplifier by the first switch. The second capacitor is characterized by a second capacitance and has a second terminal connected to the output of the amplifier by the second switch. The third capacitor connects the first and second terminals. The amplifier is configured to form a capacitive transimpedance amplifier having the third capacitor as a feedback circuit when the first switch is in a non-conducting state and the second switch is in a conducting state.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.