Method and system for quantization-free and phase-dithered fractional-N generation for phase-locked-loops
US8952736B1 · kind B1 · utility
5Cited by
5References
20Claims
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Key dates
| Filing date | Oct 9, 2013 |
| Grant date | Feb 10, 2015 |
| Priority date | — |
| Expiry date | Oct 9, 2033 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03L7/16
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A phased lock loop (PLL) including a retimer unit, rotator unit, and clock selection unit. The retimer unit is configured for sampling a divided clock generated by a divide-by-N unit with a plurality of phases of an oscillator clock generated by a ring oscillator to generate a plurality of phase shifted divide-by-N clocks. The rotator unit is configured for selectively rotating through the plurality of phase shifted divide-by-N clocks based on a constant phase shift interval, wherein the rotator unit controls a clock selection unit to produce a single output phase selected from a plurality of generated divide-by-N clock phases.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.