Clock-out amplitude calibration scheme to ensure sine-wave clock-out signal
US8952762B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Nov 22, 2010 |
| Grant date | Feb 10, 2015 |
| Priority date | — |
| Expiry date | Nov 22, 2030 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03L5/00
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A clock generator includes, in part, a buffer, a peak detector and a control logic. The buffer generates a clock output signal in response to receiving a clock signal and a feedback signal that controls the gain of the buffer. If the peak detector detects that the amplitude of the output signal is higher than the upper bound of the predefined range, the gain value applied to the variable buffer is decreased. If the peak detector detects that the amplitude of the output signal is lower than the lower bound of the predefined range, the gain value applied to the variable buffer to increased. If the peak detector detects that the amplitude of the output signal is within the predefined range, no change is made to the gain value applied to the variable buffer. The control logic generates the feedback signal in response to the peak detector's output signal.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.