Patent · US Active

Fault tolerance of multi-processor system with distributed cache

US8954790B2 · kind B2 · utility

2Cited by

8References

24Claims

0Family size

Assignee

Intel Corporation · US

Inventors

Thanunathan Rangarajan · Savanuru, IN
Baskaran Ganesan · Bengaluru, IN
Binata Bhattacharayya · Bengaluru, IN

Key dates

Filing date	Jan 4, 2011
Grant date	Feb 10, 2015
Priority date	—
Expiry date	Apr 15, 2033

Classification

Technology area (CPC G)Physics
CPC primaryG06F12/0864
WIPO fieldComputer technology
WIPO sectorElectrical engineering

Abstract

A semiconductor chip is described having different instances of cache agent logic circuitry for respective cache slices of a distributed cache. The semiconductor chip further includes hash engine logic circuitry comprising: hash logic circuitry to determine, based on an address, that a particular one of the cache slices is to receive a request having the address, and, a first input to receive notice of a failure event for the particular cache slice. The semiconductor chip also includes first circuitry to assign the address to another cache slice of the cache slices in response to the notice.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.