Microcomputer and method of operation thereof
US8954801B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Oct 15, 2010 |
| Grant date | Feb 10, 2015 |
| Priority date | — |
| Expiry date | May 2, 2031 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F1/24
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Disclosed is a microcomputer such that even when a program cannot be executed in a CPU of the microcomputer due to an external noise, an unstable power-supply voltage, and other causes, and an fatal error such as runaway occurs, returning to the original state is possible within an extremely short time while preferably avoiding initialization of the entire system. During execution of normal software processing, an interrupt signal and a reset signal are output at an arbitrary time, and if it is determined that a CPU of a microcomputer gets into a runaway state, data which has been stored in a RAM as recovery information is read out, and the CPU is recovered to the state before the runaway. Because such recovery from a fatal error occurs within a short time, software which is being executed can continue its processing as if the fatal error had not occurred.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.