Memory system and test method thereof
US8954813B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Feb 15, 2013 |
| Grant date | Feb 10, 2015 |
| Priority date | — |
| Expiry date | Apr 22, 2033 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2029/0401
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
According to one embodiment, two memory systems each including a memory and a controller are connected via a communication line. The controller includes a testing unit that performs a self-test process on the memory, a communication unit that communicates with the counterpart controller, and a status output unit. The communication unit performs a startup synchronization process which is performed before the self-test process and a termination synchronization process which is performed after the self-test process. The testing unit obtains a comprehensive test result from the test results of the two memory systems, and the status output unit of one memory system outputs the comprehensive test result.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.