Method and apparatus and record carrier
US8954941B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 3, 2010 |
| Grant date | Feb 10, 2015 |
| Priority date | — |
| Expiry date | Sep 13, 2030 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F9/30178
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Method of generating respective instruction compaction schemes for subsets of instructions to be processed by a programmable processor, comprising the steps of a) receiving at least one input code sample representative for software to be executed on the programmable processor, the input code comprising a plurality of instructions defining a first set of instructions (S1), b) initializing a set of removed instructions as empty (S3), c) determining the most compact representation of the first set of instructions (S4) d) comparing the size of said most compact representation with a threshold value (S5), e) carrying out steps e1 to e3 if the size is larger than said threshold value, e1) determining which instruction of the first set of instructions has a highest coding cost (S6), e2) removing said instruction having the highest coding cost from the first set of instructions and (S7), e3) adding said instruction to the set of removed instructions (S8), f) repeating steps b-f, wherein the first set of instructions is formed by the set of removed instructions (S9, S10).
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.