Obsolescence tolerant flash memory architecture and physical building block (PBB) implementation
US8954948B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 17, 2011 |
| Grant date | Feb 10, 2015 |
| Priority date | — |
| Expiry date | May 29, 2033 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/19105
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An electronic module and method for updating an electronic device wherein the electronic module is connected to a circuit board having one or more memory interfaces which may be embodied as processors in the electronic device. One or more semiconductor devices electrically communicate with an electrical circuit within the module. A programmable memory device including non-volatile memory electrically communicates with the electrical circuit of the electronic module. The programmable memory device includes a program having code saved therein. The code defines a multiplicity of functions for the electronic module for communication between the electronic module and a memory interface or processor of the electronic device. Electrical connection elements are attached to a substrate on a bottom side of the electronic module for electrically connecting the electrical circuit of the electronic module to the circuit board for communication between the programmable memory device and the memory interface or processor.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.