Method for detecting abnormalities in a cryptographic circuit protected by differential logic, and circuit for implementing said method
US8955160B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jul 30, 2009 |
| Grant date | Feb 10, 2015 |
| Priority date | — |
| Expiry date | Mar 3, 2030 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F21/755
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
In a method for detecting anomalies in a circuit protected by differential logic and which processes logic variables represented by a pair of components, a first network of cells carrying out logic functions on the first component of said pairs, a second network of dual cells operating in complementary logic on the second component, the logic functions being carried out by each pair of cells in a pre-charge phase placing the variables in a known state on input to the cells and followed by an evaluation phase where a calculation is performed by the cells, the method includes detecting an anomaly by at least one non-consistent state.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.