Method for manufacturing a semiconductor chip stack device
US8957457B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Nov 22, 2011 |
| Grant date | Feb 17, 2015 |
| Priority date | — |
| Expiry date | Nov 11, 2032 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/13091
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method for manufacturing a semiconductor chip stack device is provided. The method includes forming a first connecting element array on a surface of a first semiconductor chip; forming a second connecting element array on a surface of a second semiconductor chip, the second array comprising more connecting elements than the first array and the pitch of the first array being a multiple of the pitch of the second array; applying the first chip against the second chip; and setting up test signals between the first and second chips to determine the matching between the connecting elements of the first array and the connecting elements of the second array.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.