Semiconductor device

US8957502B2 · kind B2 · utility

Assignee

• FUJI ELECTRIC CO., LTD. · JP

Inventors

• Dawei Cao · Beijing, CN
• Yasuhiko Onishi · Nagano, JP

Key dates

• Filing date: Dec 12, 2012
• Grant date: Feb 17, 2015
• Expiry date: Dec 12, 2032

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10D62/393

Abstract

A semiconductor device is disclosed that has enhanced its electric charge resistance. A first parallel p-n layer is disposed in an element activating part, and a second parallel p-n layer is disposed in an element peripheral edge part. An n− surface area is disposed between the second parallel p-n layer and a first principal face. Two or more p-type guard ring areas are disposed so as to be separate from each other on the first principal face side of the n− surface area. First field plate electrodes and second field plate electrodes are electrically connected to p-type guard ring areas. Second field plate electrodes cover the first field plate electrodes adjacent to each other so as to cover the first principal face between the first field plate electrodes through a second insulating film.