SerDes jitter tolerance BIST in production loopback testing with enhanced spread spectrum clock generation circuit
US8958515B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Apr 28, 2011 |
| Grant date | Feb 17, 2015 |
| Priority date | — |
| Expiry date | Apr 1, 2033 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L7/00
- WIPO fieldMeasurement
- WIPO sectorInstruments
Abstract
A system for controllably generating jitter in a serial data stream includes a frequency generator and first and second mixers. The frequency generator is configured to output in-phase and quadrature local oscillator signals with a local oscillator frequency of at least about 5 MHz. The local oscillator frequency varies between a selectable minimum frequency and a selectable maximum frequency. The first mixer is configured to mix a fixed frequency clock signal with the in-phase local oscillator signal to output a first mixer output. The second mixer is configured to mix the fixed frequency clock signal with the quadrature local oscillator signal to output a second mixer output. An adder is configured to add the first and second mixer outputs to produce a frequency-modulated clock signal with a frequency that is about the sum of the fixed frequency and the local oscillator frequency and includes a periodic jitter.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.