Emulation system with improved reliability of interconnect and a method for programming such interconnect
US8959010B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 8, 2011 |
| Grant date | Feb 17, 2015 |
| Priority date | — |
| Expiry date | Oct 16, 2032 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F15/16
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method and apparatus for redundant communication channels in an emulation system is disclosed. A processor-based emulation system has a plurality of emulation chips on an emulation board. The emulation chips have a plurality of processor clusters. Signals are sent over one or more communication channels between processor clusters, including from a processor cluster on one emulation chip to a processor cluster on another emulation chip. Copies of the same signal may be sent in duplicate over separate communication channels. If a communication channel failure is detected, instruction memory is modified so that a processor cluster's instructions no longer address a first cluster memory location, but instead address a second cluster memory location of a non-failed communication channel. By using redundant communication channels, emulation system interconnect reliability is increased and recompilation of the design under verification may be avoided.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.