Dynamic priority control based on latency tolerance
US8959266B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Aug 2, 2013 |
| Grant date | Feb 17, 2015 |
| Priority date | — |
| Expiry date | Aug 2, 2033 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG09G5/363
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A dynamic priority controller monitors a level of data in a display engine buffer and compares the level of data in the display engine buffer to a plurality of thresholds including a first threshold and a second threshold. When the level of data in the display engine buffer is less than or equal to the first threshold, the dynamic priority controller increases a priority for processing display engine data in a communication channel. When the level of data in the display engine buffer is greater than or equal to the second threshold, the dynamic priority controller decreases the priority for processing the display engine data in the communication channel.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.