Providing a serial download path to devices
US8959274B2 · kind B2 · utility
1Cited by
17References
24Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Sep 6, 2012 |
| Grant date | Feb 17, 2015 |
| Priority date | — |
| Expiry date | Jun 24, 2033 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F13/364
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
In one embodiment, an interface may include various mechanisms to handle incoming clock and data signals. More specifically, the interface includes a first multiplexer to receive a first data signal via a serial peripheral interface (SPI) bus coupled to a first pin and a second multiplexer to receive a first clock signal via the SPI bus coupled to a second pin of the first IC and a second clock signal via an inter-integrated circuit (I2C) bus coupled to a third pin. In addition, the interface may include a decoder to receive the second clock signal and a second data signal via the I2C bus coupled to a fourth pin.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.