Facilitating gated stores without data bypass
US8959277B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 12, 2008 |
| Grant date | Feb 17, 2015 |
| Priority date | — |
| Expiry date | Jul 16, 2030 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F9/3863
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
One embodiment of the present invention provides a system that facilitates precise exception semantics for a virtual machine. During operation, the system executes a program in the virtual machine using a processor that includes a gated store buffer that stores values to be written to a memory. This gated store buffer is configured to delay a store to the memory until after a speculatively-optimized region of the program commits. The processor signals an exception when it detects that a load following the store is attempting to access the same memory region being written by the store prior to the commitment of the speculatively-optimized region.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.