Providing low-latency error correcting code capability for memory
US8959417B2 · kind B2 · utility
7Cited by
9References
23Claims
0Family size
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Key dates
| Filing date | Nov 20, 2012 |
| Grant date | Feb 17, 2015 |
| Priority date | — |
| Expiry date | Jan 30, 2033 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2029/0411
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A memory controller provides low-latency error correcting code (ECC) capability for a memory. In some implementations, the controller is configured to receive a memory access command that includes an address and a length associated with data that is to be transferred to or from the memory device, and transfer one or more bytes of data and one or more bytes of ECC information to or from locations of the memory device associated with the address and the length.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.