Fault injection of finFET devices
US8959468B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Apr 17, 2013 |
| Grant date | Feb 17, 2015 |
| Priority date | — |
| Expiry date | Apr 17, 2033 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F30/367
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Defect-describing (or “cut”) layer(s) for describing defects associated with different sides of a 3-dimensional (3D) structure enable fault modeling to determine the effect of position and location of defects on transistor performance. One or more defect-describing layers are used to identify the coordinates and sides of the 3D structures of the defects. The defect-describing layer(s) enables fault-modeling for 3D structures to understand the effects of faults on different locations, especially for defects associated with the fins of the finFET devices. Faults are injected to different locations and sides of fins and are modeled with different test vectors, test parameters and testing devices to identify detectable faults. The fault modeling would help identify the sources of defects and also improve layout design of finFET device structures.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.