Pipelined processor and compiler/scheduler for variable number branch delay slots
US8959500B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 11, 2007 |
| Grant date | Feb 17, 2015 |
| Priority date | — |
| Expiry date | Jan 11, 2031 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F9/3842
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Different numbers of delay slots are assigned by a compiler/scheduler to each different type of jump operation in a pipelined processor system. The number of delay slots is variable and kept to the minimum needed by each type of jump operation. A compatible processor uses a corresponding number of branch delay slots to exploit the difference in predictability of different types of branch or jump operations. Different types of jump operations resolved their target addresses in different numbers of delay slots. As a result, the compiler/scheduler is able to generate more efficient code than for a processor with a fixed number of delay slots for all jump types, resulting in better processor performance.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.